1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a refresh method for a semiconductor memory device.
2. Discussion of Related Art
Dynamic random access memories (DRAMs) are widely used because of their high density and relatively high speed capability. Many memory cells can be packed into a DRAM because each cell is comprised of one transistor and one capacitor of simple configurations. Each cell is smaller than those of other memory devices such as static random access memories (SRAMs).
However, in DRAM memory cells, the data stored in each cell in the form of a charge in a capacitor is lowered by leakage after a predetermined time. Thus, the DRAM memory cells need to be periodically accessed, and the data stored in the capacitor refreshed.
Meanwhile, SRAMs do not require refreshing because each cell is made of a circuit such as a flip-flop which holds the data. The flip-flops in SRAMs facilitate higher speed operation because no refresh is needed but the flip-flops occupy more space per cell and thus memory capacity is lower than DRAMs.
There are two refresh methods for DRAMs, an automatic refresh method and a self-refresh method. In the automatic refresh method, a predetermined timing interval is assigned during normal operation of the DRAM, and refresh operation is automatically performed at the assigned interval. On the other hand, a self-refresh operation is performed when the DRAM is in stand-by mode. Automatic refresh operations and self-refresh operations are well known to one skilled in the art, and thus detailed descriptions thereof will be omitted.
A pseudo static random access memory (PSRAM) has characteristics of both DRAMs and SRAMs. The PSRAM has SRAM interfaces and a memory array structure comprised of DRAM memory cells. In the PSRAM, access time for normal operation and access time for refresh operation are independently assigned within memory cell access time tRC. Thus, even though the actual access time for the normal operation is about 30-35 nano seconds, the memory cell access time tRC is set to about at least 70 nano seconds to account for the access time for the refresh operation.
If the access time for the normal operation overlaps with the access time for the refresh operation in the PSRAM, malfunctions may occur. To prevent this overlap, the access time for the normal operation and the access time for the refresh operation are independently assigned within the memory cell access time tRC.
FIG. 1 illustrates a structure of a DRAM cell array block which employs a conventional refresh method. Here, assume that, during refresh operation, a word line WL1 of a memory cell array block 100 is activated and that memory cells M11xcx9cM18 connected to bit lines BL1xcx9cBL8 and to sense amplifiers S1xcx9cS8 are accessed. During the refresh operation, if a word line WL4 of the memory cell array block 100 is activated and other memory cells M21xcx9cM28 sharing bit lines BL1xcx9cBL8 and sense amplifiers S1xcx9ch S8 are accessed for normal operation, data different from refresh data is loaded onto the bit lines BL1xcx9cBL8 and the sense amplifiers S1xcx9cS8, and malfunctions may occur.
As described above, in the conventional refresh method, the access time for the normal operation and the access time for the refresh operation are independently assigned within the memory cell access time tRC to prevent the overlap of the access time for the normal operation and the access time for the refresh operation in the same memory cell array block. As a result, a longer amount of memory cell access time tRC is needed in the conventional refresh method.
Therefore, an object of the present invention is to provide a refresh method for a semiconductor memory device capable of reducing memory cell access time and performing refresh operation normally.
Another object of the invention is to provide a refresh method for a semiconductor memory device capable of performing normal operation and refresh operation at the same time.
A refresh method according to the present invention comprises the steps of latching a low address for refresh operation when the refresh operation is requested, determining whether a normal operation command is inputted into the semiconductor memory device, comparing block selection bits of a low address for normal operation with block selection bits of the latched low address for the refresh operation when the normal operation command is inputted into the semiconductor memory device, and activating a word line for the refresh operation by decoding the latched low address for the refresh operation when the block selection bits of the low address for the normal operation are different from the block selection bits of the latched low address for the refresh operation. In a preferred embodiment, the method further comprises the steps of maintaining the latched low address for the refresh operation when the normal operation command is not inputted into the semiconductor memory device, and maintaining the latched low address for the refresh operation when the block selection bits of the low address for normal operation are the same as the block selection bits of the latched low address for the refresh operation.
In the present invention, a word line for the normal operation is activated by simultaneously decoding the low address for the normal operation while the latched low address for the refresh operation is decoded. That is, the normal operation and the refresh operation are simultaneously performed.
In one preferred embodiment, a refresh method for a semiconductor memory device comprises the steps of latching a low address for refresh operation when the refresh operation is requested; determining a mode of the semiconductor memory device; activating a word line for the refresh operation by decoding the latched low address for the refresh operation when the mode of the semiconductor memory device is a stand-by mode. In the preferred embodiment, the method further comprises the step of determining whether a normal operation command is inputted into the semiconductor memory device when the mode of the semiconductor memory device is a busy mode.